TSMC's Three Continent Fab Ramp: Arizona, Kumamoto, Dresden, and the Cost of Geographic Diversification

Arizona: from Phase 1 4 nm to a Phase 3 2 nm and A16 commitment #

TSMC Arizona Fab 21 Phase 1 began commercial volume production at 4 nm in 2024, with first revenue recognized in the fourth quarter of 2024 and customer ramp through 2025. Apple's A16 Bionic and select M-series volumes for the Mac Mini, AMD's Ryzen 9000 desktop, and Nvidia's Blackwell-derivative AI accelerators are the named lead customers in supply chain disclosures and TSMC quarterly earnings calls. Yields in 2025 reached parity with the Tainan Fab 18 Phase 1 4 nm baseline within four quarters of full-volume start, faster than the comparable 16 nm and 7 nm Taiwan ramp curves. Phase 1 capacity, originally guided at 20,000 wafer-starts per month, is on track for that target by year end 2025.

Phase 2, broken ground in 2022 and originally scheduled for 3 nm in 2028, was reconfigured in late 2023 and 2024 as a dual-node 4 nm plus 3 nm facility with first wafer outs pulled forward to 2027. The decision reflected stronger 4 nm and 3 nm demand from Apple, AMD, Qualcomm, and the AI accelerator cohort than the original 2022 demand model assumed. Phase 3, announced March 2025 alongside an incremental USD 100 billion of US commitment that lifted total TSMC US capex commitment to USD 165 billion, will bring 2 nm and A16 capacity to Arizona on a 2028 to 2029 schedule. The CHIPS and Science Act award to TSMC closed at USD 6.6 billion in direct grants and up to USD 5 billion in loans against the original commitment, before the March 2025 expansion announcement, which negotiates additional incentive support.

Kumamoto JASM: the Sony and Denso joint venture as Japan's chip revival anchor #

Japan Advanced Semiconductor Manufacturing, the JV with Sony Semiconductor Solutions (20 percent), Denso (10 percent), and TSMC majority, broke ground April 2022 in Kumamoto Prefecture and reached volume production in February 2024, ahead of the original 2024 H2 schedule. Phase 1 produces image sensor controllers, automotive microcontrollers, and a portion of Sony's CMOS image sensor logic at 12 nm, 16 nm, 22 nm, and 28 nm nodes. Sony pre-committed approximately 50 percent of Phase 1 output for its image sensor business; Denso committed roughly 10 to 15 percent for automotive chips. Phase 2, announced in February 2024 and ground broken December 2024, expands the Kumamoto cluster with 6 nm and 7 nm capacity for Sony, Denso, and Toyota electrification supply.

The Japanese government's industrial policy support has been the most generous of any TSMC overseas project as a fraction of capex. METI committed approximately JPY 476 billion (USD 3 billion at then-prevailing rates) to Phase 1 against a roughly JPY 1.1 trillion total project cost, then layered an additional JPY 732 billion (USD 4.9 billion) for Phase 2. The cluster has triggered the largest greenfield wage adjustment in Kumamoto in decades, with surrounding prefectures running labor pull dynamics into automotive and electronics suppliers. Rapidus, the separate Japanese consortium pursuing 2 nm at the Chitose, Hokkaido site with IBM technology transfer, runs a parallel but distinct path: state-led, leading-edge, with first 2 nm pilot wafers targeted Q2 2025 and volume in 2027. The two anchor projects together represent Japan's most concentrated semiconductor industrial policy effort since the 1980s.

Dresden ESMC: the EU Chips Act and the automotive customer base #

European Semiconductor Manufacturing Company, the JV with Bosch (10 percent), Infineon (10 percent), NXP (10 percent), and TSMC majority (70 percent), broke ground August 2024 in Dresden, Saxony. The fab targets 28 nm, 22 nm, and 16 nm nodes for automotive and industrial customers, with first volume production scheduled for 2027. The German federal government, under the EU Chips Act and the EU State Aid framework, committed approximately EUR 5 billion in direct subsidy against a project cost above EUR 10 billion. The ESMC structure reflects the EU's strategic priority to localize automotive-grade chip supply after the 2020 to 2022 automotive shortage that idled European auto production lines.

The fab is mature-node by design, not leading-edge. The decision is consistent with the European customer base: Bosch, Infineon, NXP, and STMicroelectronics need 28 nm, 22 nm, and 16 nm logic, power, and analog volumes, not 3 nm or 2 nm leading-edge. The Saxony cluster, anchored by GlobalFoundries Dresden, Infineon's existing Dresden fab, X-Fab, and the new ESMC site, makes Dresden one of two European semiconductor manufacturing centers (alongside Crolles, France, where STMicroelectronics and GlobalFoundries are expanding). The EU Chips Act target of doubling EU semiconductor manufacturing share to 20 percent of global by 2030 is unlikely to be met on the original timeline; ESMC and the Crolles expansions get the share to perhaps 12 to 14 percent by 2030 on industry tracking, which is a real shift even if short of the headline target.

The unit economics: capex per wafer and yield curve catch up #

TSMC's own management commentary on the second-quarter and third-quarter 2024 earnings calls placed Arizona Phase 1 4 nm capex per wafer between 30 and 50 percent above the Tainan Fab 18 4 nm baseline. The drivers are construction labor cost, equipment installation cost, regulatory and permitting overhead, supply chain logistics for chemicals and gases, and the scale-out from a single-fab footprint versus the dense Tainan cluster. The cost gap is real and not yet closing materially. TSMC has pushed price increases through the customer base on Arizona-produced volumes; the price premium has been accepted by customers willing to pay for geographic diversification, but not by the full customer book.

The yield curve did catch up faster than the cost curve. By second-half 2025, Arizona Phase 1 4 nm yields ran within roughly 1 to 2 percentage points of Tainan's mature 4 nm yields per supply-chain disclosures and TSMC commentary. The implication is that the geographic diversification cost premium is structural in capex (and therefore in depreciation per wafer) rather than operational. The customers willing to pay the premium are those with strategic concentration risk concerns: Apple, AMD for select SKUs, the AI accelerator cohort with US export-control sensitivity, and the defense and aerospace allocation that DOD and the Office of Strategic Capital have negotiated separately.

Customer allocation and the geographic premium pricing #

Apple is the largest single Arizona Phase 1 customer by revenue, with M-series Mac Mini, A16 Bionic for older iPhone SKUs, and select chipset volumes ramping through 2024 and 2025. AMD's Ryzen 9000 desktop and select EPYC server SKUs use Arizona Phase 1 4 nm volume, with capacity allocation negotiated on top of TSMC's standard customer agreements. Nvidia's Blackwell-derivative HGX volumes, where US export control compliance and customer concentration risk sit highest, have been confirmed as Arizona Phase 2 customers per the March 2025 announcement. The DoD Office of Strategic Capital has reserved a fraction of Arizona output for trusted-foundry use, with the specific allocation classified.

The pricing premium has been accepted by these customers but at a discount to TSMC's initial ask. Industry channel checks suggest 5 to 12 percent gross price premium for Arizona-produced volumes versus Tainan-produced volumes, against TSMC's reported 30 to 50 percent capex per wafer disadvantage. The implication is that TSMC is absorbing the gap on a near term basis, with the expectation that the CHIPS Act ITC (25 percent of qualified capex), state and local incentives, and yield curve maturation collectively close most of the gap by Phase 3. The unresolved question is what happens at the Phase 2 and Phase 3 ramps if construction cost inflation persists. Hercules tracks construction-cost inflation, equipment lead times, and supply chain logistics indicators that drive the gap.

What this means for sovereign chip strategy and the 2027 to 2030 build #

The first-order conclusion is that geographic diversification of leading-edge logic manufacturing is happening, but at a unit cost above the Taiwan baseline that customers are absorbing through a combination of premium pricing, government subsidy capture, and TSMC margin compression. The CHIPS Act award structure, by funding a fraction of qualified capex against grant and ITC, materially reduces the long-run cost gap on a depreciation basis. The EU Chips Act subsidy intensity is comparable; the Japanese METI subsidy intensity for JASM Phase 1 was the highest of the three. The competitive question is whether Samsung Foundry's Taylor, Texas fab and Intel Foundry's Arizona expansion close their portion of the diversification market, or whether TSMC retains the foundry-of-choice status in the diversified geography.

For 2027 to 2030, the Arizona Phase 3 2 nm and A16 commitment, the Kumamoto Phase 2 6 nm and 7 nm production, and the Dresden ESMC mature-node start collectively bring TSMC's overseas wafer-start capacity to roughly 12 to 15 percent of the company's total monthly capacity by 2030, against roughly 6 percent in 2024. The structural shift is real. The Taiwan concentration on leading-edge nodes (3 nm and 2 nm) declines but does not collapse; Tainan and Hsinchu remain the engineering and yield-curve anchor for the foreseeable future. The strategic implications for the Taiwan strait risk pricing, the US allied-supply base, and the leverage that allied governments have on TSMC's roadmap are first-order. Argus and Strategos track the fab schedules, the customer allocation cycles, and the political risk overlay on each project.

Sources #

• TSMC investor relations and quarterly earnings
• US Department of Commerce CHIPS Program Office
• METI Japan semiconductor strategy
• European Commission Chips Act portal
• TSMC Arizona facility news
• Sony Semiconductor Solutions JASM updates
• Bosch and Infineon ESMC press releases
• Reuters semiconductor coverage
• Nikkei Asia chip industry coverage
• Apple supply chain filings (Apple Newsroom)
• AMD investor relations
• Nvidia investor relations