Industry

Semiconductors

Trade-flow, capex ROI, and policy analytics for fabs, fabless designers, OSAT, equipment, and materials.

Framing

The semiconductor industry is being restructured along three orthogonal axes simultaneously: the AI demand supercycle, the CHIPS-era reshoring of leading-edge logic, and the export control regime on advanced compute to China. Each axis has its own analytical cadence, its own data primary sources, and its own decision owner inside a fab, fabless designer, OSAT, equipment vendor, or materials supplier.

What the consultancy contributes is integrated work across these axes: the BACI HS 8541 and 8542 trade panel, WITS tariff lines, CEPII gravity, MLPerf performance benchmarks, SemiAnalysis and Epoch AI compute trends, and the CHIPS Act award ledger. The recent flagship brief, on the Taiwan share that went up rather than down, is an example of the work shape: long form, replicable, and defensible against the press narrative.

Engagements typically run as named studies for a strategy or government affairs team, with rolling retainer options for groups that need recurring quantitative bench.

Decisions we inform

  • Forecasting reshoring signals in HS 8542 import composition by exporter and subheading.
  • Building advanced packaging exposure scenarios for OSAT operations in Malaysia and Vietnam.
  • Modeling chip generation cost curves and ROI under named procurement assumptions.
  • Mapping CHIPS award stacking across Section 48D, DOE, and state incentives.
  • Quantifying export control exposure for advanced compute SKUs into restricted geographies.
  • Briefing trade associations on industry-wide tariff and policy implications.

Named offerings

HS 8542 Trade Diagnostic

Six to eight week deep-read of US chip import data by exporter, subheading, and use case. Includes equipment-import lead indicator parsing on HS 848610 and 848620.

Advanced Packaging Exposure

Four to six week assessment of a company or asset's exposure to the Taiwan-direct versus Malaysia-OSAT packaging shift. Volume, margin, and timeline scenarios.

Compute Cost Curve

Standard study, customizable for fabless, hyperscaler, or PE consumers. Effective FLOPs per dollar across chip generations and procurement models.

CHIPS Stacking Memo

Three to five week incentive-stacking analysis for a planned investment. CHIPS direct grant, Section 48D, DOE Title XVII, state grants, utility riders.

Export Control Risk Map

Quarterly subscription tracking the BIS export control regime, license issuance patterns, and downstream compute SKU exposure.

Sample questions

  • Where does the BACI data say our advanced packaging volume actually flows in the Taiwan to Malaysia to US chain, and how does that change with TSMC Arizona Phase 2?
  • Walk us through what 2027 reshoring signals will look like in the HS 8542 memory subheadings versus advanced logic.
  • We are sizing a $4 billion fab investment in Arizona. What does the realistic incentive stack and ROI look like under the latest BIS rules and DOE programs?
  • Build us a defensible quarterly export control brief tracking the BIS license issuance pattern for our HS 854231 and 854232 SKU lines.
  • Our trade association needs to brief Commerce on the OSAT shift. Can you build the panel data behind that?