India's Silicon Pivot: ISM 1.0 to 2.0, Tata in Dholera, and the Modi 3.0 Compute Policy Stack

ISM 1.0: The Baseline Outlay and the First Approval Cohort #

The India Semiconductor Mission was notified by the Ministry of Electronics and Information Technology (MeitY) on 21 December 2021 with a headline outlay of INR 76,000 crore (roughly USD 10 billion). The outlay covers four schemes: a fab fiscal support program at up to 50 percent of project cost, a display fab program at up to 50 percent, a compound semiconductor and ATMP scheme revised upward to 50 percent of capex in September 2022, and a design-linked incentive program of INR 1,000 crore for fabless startups. The mission sits inside Digital India Corporation as a Section 8 vehicle, with sanctioning power at the Union Cabinet on MeitY's recommendation.

Through 2022 and most of 2023, progress was modest. The Vedanta and Foxconn JV announced in September 2022 lapsed in mid 2023, and the ISMC consortium with Tower Semiconductor stalled when Intel's announced acquisition of Tower paused commitments. The reset arrived on 29 February 2024, when the Cabinet approved three projects in a single sitting: Tata Electronics with Powerchip Semiconductor Manufacturing Corporation (PSMC) for a wafer fab at Dholera, Gujarat at INR 91,000 crore, Tata Semiconductor Assembly and Test at Jagiroad, Assam at INR 27,000 crore, and CG Power with Renesas and Stars Microelectronics at Sanand at INR 7,600 crore. Micron's ATMP at Sanand at USD 2.75 billion, sanctioned in June 2023, was already in construction. The Foxconn and HCL Group JV at INR 3,706 crore, approved January 2025, completed the first cohort. Across the five projects, ISM 1.0 commitments sum to approximately INR 1.55 lakh crore in announced capex and roughly INR 60,000 to 65,000 crore in central subsidy, before state support.

Tata Electronics at Dholera: India's First Commercial Wafer Fab #

The Tata Electronics fab at Dholera Special Investment Region is the centrepiece of ISM 1.0 and the first commercial scale wafer fab sanctioned in India after four decades of false starts. The plant is being built in two phases on a 160 acre parcel, with PSMC of Taiwan supplying the process technology under a multi-year licence and engineering support agreement. Phase one targets 50,000 wafer starts per month at 28nm and 40nm logic plus mature node mixed signal, with sample production scheduled for late 2026 and commercial output in 2027. Phase two, gated on phase one ramp, would extend the node mix toward 22nm and add 50,000 wafer starts. The 28nm choice is deliberate: it captures the largest pool of automotive, power management, and IoT demand outside the leading-edge race, and avoids extreme ultraviolet lithography constrained by US and Dutch export controls.

Public subsidy under the modified fab scheme is 50 percent of project cost, split between the centre and Gujarat. Gujarat adds capital subsidy, water allocation, and a dedicated power line from the Dholera grid spur. The Tata ATMP at Jagiroad complements the front end by closing assembly and test. Jagiroad sits inside the Tezpur and Morigaon corridor, with land allotted by the Assam Industrial Development Corporation. Full ramp targets roughly 48 million chips per day across automotive, mobile compute, and consumer applications. The Assam siting is politically symbolic, the first major semiconductor investment east of the Brahmaputra, and operationally tied to the Northeast logistics build under PM Gati Shakti. Tata Electronics has begun early offtake conversations with automotive OEMs and consumer electronics brands in India and Southeast Asia, with the policy aim that initial output substitutes part of the USD 24 billion in semiconductor imports India recorded in fiscal 2024 (Ministry of Commerce data).

Micron, Foxconn HCL, CG Power, and Kaynes: The Back End Cluster #

Micron Technology was the first major foreign semiconductor firm to commit under ISM, with the Cabinet approving its USD 2.75 billion ATMP at Sanand in June 2023. The split is approximately USD 825 million in Micron capital and USD 1.93 billion in central and state subsidy under the modified scheme. Phase one of 500,000 square feet broke ground in September 2023 and Micron's chief executive announced first packaged DRAM and NAND output by the end of calendar 2024 in the company's fiscal 2024 10-K filing. The Sanand site is targeted at memory packaging and test, with output flowing into Micron's global mobile, automotive, and data center supply chains rather than the Indian merchant market.

Foxconn and HCL Group's JV, approved in January 2025 at INR 3,706 crore for a Jewar facility in Uttar Pradesh, focuses on display driver IC packaging and test, an area where India currently imports nearly 100 percent of demand. CG Power with Renesas of Japan and Stars Microelectronics of Thailand is building an OSAT at Sanand at INR 7,600 crore with capacity targeted at 15 million chips per day across automotive, industrial, and consumer power management lines. Kaynes Semicon, a Bengaluru and Mysuru based electronics manufacturing services group, received Cabinet approval in September 2024 for an INR 3,307 crore ATMP at Sanand at 6.3 million chips per day. Tower Semiconductor of Israel held discussions with Adani Group through March 2025 for a potential analog and mixed signal fab at Taloja in Maharashtra, with reported project value of USD 10 billion, but no Cabinet sanction has been issued at time of writing.

ISM 2.0: The Modi 3.0 Incremental Phase #

With the original INR 76,000 crore ISM 1.0 envelope effectively committed across the five approved projects, the Union Cabinet signalled in July 2024 that an ISM 2.0 phase would be notified, with media reporting an additional outlay in the range of INR 60,000 to 70,000 crore under consideration in the Department of Expenditure. MeitY officials at Semicon India 2024 in Greater Noida (11 to 13 September 2024) referenced industry commitments from over 250 companies and the queue of pending applications including Tower with Adani, the Zoho Corporation fab proposal, and a second Tata phase at Dholera. The political logic of ISM 2.0 is that the first cohort exhausted the headline 50 percent capex subsidy pool faster than originally scheduled, and Modi 3.0's coalition government wants visible investment continuity into 2027 ahead of state polls in Gujarat, Assam, Maharashtra, and Uttar Pradesh.

The structure of ISM 2.0 under discussion as of early 2026 is reported to extend the 50 percent fiscal support for fabs and ATMPs, add a new line item for compound semiconductors including silicon carbide and gallium nitride power devices that are critical to electric vehicle traction inverters, and expand the design-linked incentive cap. Materials, gases, photoresists, and equipment ecosystem development are reported to be a separate strand, recognising that a fab without local high purity chemicals and gases would import its bill of materials from Singapore, Taiwan, and Japan and remain structurally dependent on those supply chains. The Department for Promotion of Industry and Internal Trade is also engaging with the United States under the iCET initiative for joint workforce and equipment supply chain initiatives, including a memorandum of understanding signed in March 2024.

Design-Linked Incentive, Materials, and the Adjacent PLI Stack #

Beyond fabs and ATMPs, India's compute industrial policy operates through three reinforcing programs. The design-linked incentive (DLI) of INR 1,000 crore, also notified in December 2021, supports 100 domestic chip design startups across 25 product design and 75 deployment-linked grants, with C-DAC as the implementation agency. As of FY 2025 disclosures, MeitY has approved 22 DLI cohorts including Saankhya Labs, Mindgrove Technologies, and Calligo Technologies, with cumulative grants in the INR 350 crore range and an extension under discussion to lift the cap to INR 5,000 crore as part of ISM 2.0. The Semicon India design challenge, announced at Semicon India 2024, supplements DLI with milestone-linked equity grants and tape-out subsidies for 100 academic and corporate teams.

Materials supply chain investment is the quietest but most strategically consequential strand. Mosaic Materials and Avantor's Singapore expansion announced in 2024 includes capacity dedicated to Indian fab demand for high purity solvents, photoresist precursors, and slurries, with Avantor's facility supplying Sanand and Dholera through 2027. Linde, Air Liquide, and Air Products have all committed to industrial gas plants colocated with the Sanand cluster. Adjacent to the chip programs, the advanced cell chemistry (ACC) PLI of INR 18,100 crore, notified in 2021 and expanded in 2024, has anchored battery cell capacity through Reliance New Energy, Ola Electric, and Rajesh Exports as initial winners, with a second tranche of 30 GWh in late 2024 going to Reliance, ACC Energy Storage, and Waaree. The displays mission, a separate proposal under MeitY review since 2023, would extend the fab fiscal support framework to thin film transistor and active matrix organic light emitting diode panels, but no Cabinet approval had been issued as of the most recent PIB releases.

The 2030 Capacity Envelope and the Strategos Read #

Aggregating the approved cohort, India's wafer capacity at Dholera phase one ramp will reach roughly 50,000 wafer starts per month at 28nm and mature nodes by 2027, expandable to 100,000 by decade end if phase two is sanctioned. ATMP and OSAT capacity at Sanand, Jagiroad, and Jewar combined targets approximately 100 million chips per day at full ramp, roughly 3 percent of global packaging by units, skewed toward mature nodes, memory, and display drivers. India Electronics and Semiconductor Association projects domestic demand at USD 100 to 110 billion by 2030 from USD 38 billion in 2023, with domestic output substituting an estimated 12 to 18 percent of demand by 2030 in the central case.

Strategos, our industrial policy and compute strategy platform, models three scenarios. In the on-schedule case (45 percent probability), Tata Dholera ramps on time, ISM 2.0 is notified by end 2026 at roughly INR 65,000 crore, and a Tower-Adani style compound semiconductor deal closes, putting India on a path to USD 25 billion in domestic output by 2030. In the slip case (40 percent probability), water and equipment delivery delays push Dholera commercial output to 2028 and output reaches USD 14 to 16 billion. In the upside case (15 percent probability), a Tower deal closes, a second foreign 28nm partner is secured, and the displays mission is approved, lifting output toward USD 32 billion. The binding variables are not subsidy rupees, which are committed, but skilled process engineers (Skill India targets 85,000 by 2030), high purity water in Gujarat, and equipment supply where ASML, Applied Materials, Lam Research, and Tokyo Electron gate the tooling pace. For multinational chief executives, 2027 is the earliest realistic window for commercial Indian wafers, ATMP capacity is already ramping, and the chemicals, gases, and equipment service ecosystem is the more accessible near-term entry point.

Sources #

• MeitY notification of India Semiconductor Mission, December 2021
• Press Information Bureau release on Cabinet approval of three semiconductor projects, 29 February 2024
• India Semiconductor Mission portal, project status
• Tata Electronics announcement on Dholera fab and Jagiroad ATMP
• Micron Technology Form 10-K fiscal year 2024, Sanand ATMP disclosure
• Powerchip Semiconductor Manufacturing Corporation 2024 annual report on India technology partnership
• Reuters, Tower Semiconductor in talks with Adani for India fab, March 2025
• Mint coverage of Foxconn HCL JV approval, January 2025
• Economic Times reporting on ISM 2.0 outlay deliberations, 2024 and 2025
• Press Information Bureau release on Semicon India 2024, 11 to 13 September 2024
• Ministry of Heavy Industries notification on advanced cell chemistry PLI of INR 18,100 crore
• India Electronics and Semiconductor Association demand outlook 2023 to 2030